1. Field of the Invention
The present invention relates to a tri-state bus structure. In particular, the present invention relates to a tri-state bus amplifier-accelerator for driving long and heavily loaded busses.
2. Discussion of the Related Art
Bus structures for carrying data or control signals are generally long and connected to and through a significant number of circuits and subsystems. Thus, capacitance associated with such bus structures are appreciable. Careful design of such bus structures is necessary to ensure performance.
In a conventional integrated circuit, size of a bus driver increases with the length, load, and speed of a bus. However, the size of a bus driver cannot increase without limitations. First, the silicon area required for a large driver is significant. In addition, multiple levels of pre-drivers are necessary to provide a large bus driver, leading to further requirements in silicon area. Furthermore, a long bus has a long propagation delay.
Bus design has thus an adverse feedback problem--i.e., a bus having a large number of drivers and receivers has a large capacitance, thus requiring larger drivers, which in turn further increases the capacitance, requiring still larger drivers and incurring further pre-driver delays.
One source of capacitance is the parasitic capacitance of a transistor. The drive of a transistor increases linearly with its channel width, which also increases parasitic capacitance.
What is needed is a bus structure that does not require progressively larger drivers for additional load. Furthermore, what is needed is a driver structure that minimizes the driver size as well as the propagation delays.